library verilog;
use verilog.vl_types.all;
entity total is
    port(
        rst             : in     vl_logic;
        clk             : in     vl_logic;
        out1            : out    vl_logic_vector(6 downto 0);
        out2            : out    vl_logic_vector(6 downto 0);
        h               : out    vl_logic_vector(3 downto 0);
        l               : out    vl_logic_vector(3 downto 0)
    );
end total;
